FPGA Design UART BAUD Rate Generator

FPGA UART module for Digital Device Design  

                     Design BAUD Rate Generator

In many applications it is required to have an peripheral communication to communicate to the outer world. Here my consideration involves Universal Asynchronous Receiver Transmitter (UART) module widely known as RS232 communication procedure. RS232 communication is widely adopted within short distance which also faster communication procedure. Here, my consideration is high speed UART module having baud rate 115200 bit per second (bps). FPGA is nice to build necessary UART component inside using it Logic Element (LB) in terms of logic gates. 

Before proceeding Transmitter and Receiver Module it is required to have a clock generation, well known as baud rate generator and primary objective is to provide transmitter or receiver clock. Once baud rate generator is completed then it is possible to share this module among the transmitters and receivers.  So the freedom comes, we can have multiple UART system coupled within a Digital system and all are working in parallel mode- similar to combinational logic circuit.

Designing Baud Rate Generator:

                                      

Here, I design hypothetically a digital system where two TxD pin are used to transmit data and one RxD pin is used to receive, they shared same Clock generated by Baud Rate Generator. Transmitters and Receiver are independent module, they have their own 8 bit data register. These are achieved by using VHDL components – a structural design approach.

Primary Philosophy is remind that Baud rate  generator clock should be 16 times more than the actual baud rate. We need to calculate a comparator coefficient which can be achieved as below,

 Coff= ( FPGA Clk Freq. )/(16*115200)

Inside the VHDL architecture it is required to design a process which will execute each time FPGA clock value changes, an event [ref. sensitivity list] and each desired clock value [rising edge or falling edge] counter value will be incremented. If it reaches Coff value that is calculated above,  Baud rate clock tick will be changed ‘1’ and the next cycle it will be retain to ‘0’.

Pseudo code will looks like that

Entity name is

Use Generic global definition such as

Generic(

Fpga_clok :type :=clock value;

baudrate :type :=desired baud rate

);

Port(

Identifier: mode type

);

Using Generic it is possible to reuse code for different FPGA CLOCK and can produce different BAUD RATE

Architecture

Signal definition:

begin

baudrate : Process(sensitivity list[clock])

Begin

 If Reset =’1’ then clear all internal value such coff and counter

Else If counter = coff. Then the Baudrate tick =’1’

Else Baudrate tick =’0’ and increment counter.

End process baudrate;

       

System is written in VHDL for Cyclone IV E FPGA using Quartus II IDE and Simulated using MODEL SIM. Out put becomes valid after next clock cycle due to the signal assignment.  

RTL view : 

Simulation result presented below :