Serial Communication Protocol probably the most common communication protocol and many system adopt this one. Main stream of the Serial protocol are

1.       Each clock cycle only one signal will be transferred or received.

2.        Start condition initiates a communication, a transition between High to Low (TTL)

3.        Data can be sent in a number of bits, i.e 8 bits

4.       Stop bit terminates data communication  transmission line back to high  (TTL)

5.       Optional parity bit use for data validation

6.       Data transmitted   from LSB to MSB

7.       IDLE  State transmission line back to high  (TTL)

StartCondition|BIT_LSB|NEXT_BIT…     MSB_BIT|PARITY_BIT|StopCondition

 In my consideration the Serial Data Length is 8bit and currently no hardware handshaking.

Main stream of the soft core may consider

1.       State machine to receive data bit

2.       A state pin which indicates the core is in busy state  

3.       Interrupt pin should have a short state transition indicates a successful data transfer.

4.       Data buffer to store data temporary

If PC serial use to communicate with FPGA then a  TTL to Serial converter must be consider. I consider Altera FPGA GPIO pin which provides TTL 3.3V logic level.

                           My RTL view of the transmitter looks like

I transmit continuous string “FPGAIV” where IV stands for Altera Cyclone IV and using serial terminal such putty I received

                           

FPGA Design UART BAUD Rate Generator

FPGA UART module for Digital Device Design  

                     Design BAUD Rate Generator

In many applications it is required to have an peripheral communication to communicate to the outer world. Here my consideration involves Universal Asynchronous Receiver Transmitter (UART) module widely known as RS232 communication procedure. RS232 communication is widely adopted within short distance which also faster communication procedure. Here, my consideration is high speed UART module having baud rate 115200 bit per second (bps). FPGA is nice to build necessary UART component inside using it Logic Element (LB) in terms of logic gates. 

Before proceeding Transmitter and Receiver Module it is required to have a clock generation, well known as baud rate generator and primary objective is to provide transmitter or receiver clock. Once baud rate generator is completed then it is possible to share this module among the transmitters and receivers.  So the freedom comes, we can have multiple UART system coupled within a Digital system and all are working in parallel mode- similar to combinational logic circuit.

Designing Baud Rate Generator:

                                      

Here, I design hypothetically a digital system where two TxD pin are used to transmit data and one RxD pin is used to receive, they shared same Clock generated by Baud Rate Generator. Transmitters and Receiver are independent module, they have their own 8 bit data register. These are achieved by using VHDL components – a structural design approach.

Primary Philosophy is remind that Baud rate  generator clock should be 16 times more than the actual baud rate. We need to calculate a comparator coefficient which can be achieved as below,

 Coff= ( FPGA Clk Freq. )/(16*115200)

Inside the VHDL architecture it is required to design a process which will execute each time FPGA clock value changes, an event [ref. sensitivity list] and each desired clock value [rising edge or falling edge] counter value will be incremented. If it reaches Coff value that is calculated above,  Baud rate clock tick will be changed ‘1’ and the next cycle it will be retain to ‘0’.

Pseudo code will looks like that

Entity name is

Use Generic global definition such as

Generic(

Fpga_clok :type :=clock value;

baudrate :type :=desired baud rate

);

Port(

Identifier: mode type

);

Using Generic it is possible to reuse code for different FPGA CLOCK and can produce different BAUD RATE

Architecture

Signal definition:

begin

baudrate : Process(sensitivity list[clock])

Begin

 If Reset =’1’ then clear all internal value such coff and counter

Else If counter = coff. Then the Baudrate tick =’1’

Else Baudrate tick =’0’ and increment counter.

End process baudrate;

       

System is written in VHDL for Cyclone IV E FPGA using Quartus II IDE and Simulated using MODEL SIM. Out put becomes valid after next clock cycle due to the signal assignment.  

RTL view : 

Simulation result presented below :

 

Build ARCH LINUX package into Debian

SVOX –PICO,

 Build  ARCH LINUX  package into Debian ARM 6/7

Svox – pico is small foot print for test to speech engine which is free to download from

AUR distribution. To compile it at arm 6/7 it requires a patch which is also available to download form AUR site. For more details about this package please read the following link

https://aur.archlinux.org/packages/svox-pico-git/?setlang=en

To patch a package is a easy task when the patch is available. This document only the patching way which may be useful for a new linux user.  I explained it step by step .

Step 1. Download tarball of the patch and svox-pico from AUR site which is referenced above.

Step 2. Extract the main package and the patch, you may use tar command to extract.

Step 3. Copy the content of  patch directory into the directory svox package   where you have just extracted. As an example I extracted svox-pico  into pico directory and patch into patch directory.

So, I need to copy the patch (lm.patch) file to this directory as below

       sudo cp /pathtodirectory/patch/lm.patch  /pathtodirectory/svox-picopico/lm.patch

Step 4. Now it is needed to install another library, libtool.

             sudo apt-get install libtool

Step 5. Now it is time to do patch. To do it is required to enter into the directory

            where I have saved package. I have use these command sequentially to build and

            install in debian linux system.

cd /pathtodirectory/svox-picopico/

patch -p2 < ./lm.patch

            ./autogen.sh

./configure --prefix=/usr       

I received output message as

checking for a BSD-compatible install... /usr/bin/install -c

checking whether build environment is sane... yes

checking for a thread-safe mkdir -p... /bin/mkdir -p

checking for gawk... no

checking for mawk... mawk

checking whether make sets $(MAKE)... yes

……..

when this process is finished it is required to invoke make. It is simple just write make in the console. I receive the following output.

  make

  CC     picoacph.lo

  CC     picoapi.lo

  CC     picobase.lo

  CC     picocep.lo

  CC     picoctrl.lo

…………….

Then I fixed where to install this build package. It should be /usr/lib/arm_version

            export LIB_DIR==/usr/lib/arm-linux-xxx

sudo make LIBDIR=${LIB_DIR} install

make[1]: Entering directory  

 /bin/mkdir -p '/usr/lib'

 /bin/bash ./libtool   --mode=install /usr/bin/install -c   libttspico.la '/usr/lib'

libtool: install: /usr/bin/install -c .libs/libttspico.so.0.0.0 /usr/lib/libttspico.so.0.0.0

libtool: install: (cd /usr/lib && { ln -s -f libttspico.so.0.0.0 libttspico.so.0 || { rm -f libttspico.so.0 && ln -s libttspico.so.0.0.0 libttspico.so.0; }; })

libtool: install: (cd /usr/lib && { ln -s -f libttspico.so.0.0.0 libttspico.so || { rm -f libttspico.so && ln -s libttspico.so.0.0.0 libttspico.so; }; })

libtool: install: /usr/bin/install -c .libs/libttspico.lai /usr/lib/libttspico.la

libtool: install: /usr/bin/install -c .libs/libttspico.a /usr/lib/libttspico.a

libtool: install: chmod 644 /usr/lib/libttspico.a

libtool: install: ranlib /usr/lib/libttspico.a

libtool: finish: PATH="/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/sbin" ldconfig -n /usr/lib

----------------------------------------------------------------------

 Step 6. sudoo reboot 

         svox-pico is now installed ,

                            PROCESS LIST : ps COMMAND
In embedded linux system It is often required to see the list of process which is running on the embedded linux system . In linux it is possible to generate a process  list by writing the following command.
ps  -[option ]
option consist of
-a : list of information about all the process except group loader/process
-A : list of information of all the process
-e :  list of information of all the process which are running
-d: list of information about all the process except session loader
-f : generate a full list
-j : list of session id and group id
-l : generate a long list

it is often used one or more option in together.  Most of the cases I use ps -ef  command to generate a
list which contain all the process those are running
More nicely
ps -ef | grep process_name_to see > processname.txt

which will write the desired process status into destination file.