Serial Communication Protocol probably the most common communication protocol and many system adopt this one. Main stream of the Serial protocol are

1.       Each clock cycle only one signal will be transferred or received.

2.        Start condition initiates a communication, a transition between High to Low (TTL)

3.        Data can be sent in a number of bits, i.e 8 bits

4.       Stop bit terminates data communication  transmission line back to high  (TTL)

5.       Optional parity bit use for data validation

6.       Data transmitted   from LSB to MSB

7.       IDLE  State transmission line back to high  (TTL)

StartCondition|BIT_LSB|NEXT_BIT…     MSB_BIT|PARITY_BIT|StopCondition

 In my consideration the Serial Data Length is 8bit and currently no hardware handshaking.

Main stream of the soft core may consider

1.       State machine to receive data bit

2.       A state pin which indicates the core is in busy state  

3.       Interrupt pin should have a short state transition indicates a successful data transfer.

4.       Data buffer to store data temporary

If PC serial use to communicate with FPGA then a  TTL to Serial converter must be consider. I consider Altera FPGA GPIO pin which provides TTL 3.3V logic level.

                           My RTL view of the transmitter looks like

I transmit continuous string “FPGAIV” where IV stands for Altera Cyclone IV and using serial terminal such putty I received